<?xml version="1.0" encoding="UTF-8"?><rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
	xmlns:media="http://search.yahoo.com/mrss/"
		>
<channel>
	<title>Comments on: So, Does Anyone Even Use All These Darn CPU Instructions?</title>
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	<link>http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/</link>
	<description>Programming language geek-outs with your host, Max Bolingbroke</description>
	<lastBuildDate>Wed, 22 Apr 2009 11:47:14 +0000</lastBuildDate>
	<generator>http://wordpress.com/</generator>
	<sy:updatePeriod>hourly</sy:updatePeriod>
	<sy:updateFrequency>1</sy:updateFrequency>
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		<title>By: Anonymouse</title>
		<link>http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-729</link>
		<dc:creator>Anonymouse</dc:creator>
		<pubDate>Wed, 20 Aug 2008 11:18:00 +0000</pubDate>
		<guid isPermaLink="false">http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-729</guid>
		<description>cmp has a higher count than jz because cmp is used with all types of jump instructions, so you should compare cmp  jz+jnz+jg+jl+jge+jle+jb+...

Also note that add eax,1 may be faster than inc eax on modern out-of-order architectures since inc does a partial flags update (so it must wait for the previous flag update to complete), see the Intel optimization manual for Core 2 on this.</description>
		<content:encoded><![CDATA[<p>cmp has a higher count than jz because cmp is used with all types of jump instructions, so you should compare cmp  jz+jnz+jg+jl+jge+jle+jb+&#8230;</p>
<p>Also note that add eax,1 may be faster than inc eax on modern out-of-order architectures since inc does a partial flags update (so it must wait for the previous flag update to complete), see the Intel optimization manual for Core 2 on this.</p>
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		<title>By: jkoss</title>
		<link>http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-693</link>
		<dc:creator>jkoss</dc:creator>
		<pubDate>Thu, 06 Dec 2007 04:09:23 +0000</pubDate>
		<guid isPermaLink="false">http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-693</guid>
		<description>&#039;dec&#039; would also be common because of the frequency of code using (expression) - 1  

for-instance..

..given a pointer to buffer and its size the last item is at (pointer + size) - 1 

..the previous item in an array is at (index) - 1

Also I dont agree with the conjecture that most loops are from 0 (or 1) to n..

..most loops are simply repeated &#039;n&#039; times .. thus &#039;n&#039; itself can be used as the counter, requiring only 1 register of overhead instead of the 2 registers needed for &#039;0 to n&#039; style loops.

If you are suprised that C compilers can turn your 0 to n style loop into something different, think again. Modern compilers will even turn code using several incrementing/decrementing pointers into code using a single incrementing/decrementing pointer plus an invariant displacement. Same number of registers needed, but only one increment per iteration instead of 2 or more.</description>
		<content:encoded><![CDATA[<p>&#8216;dec&#8217; would also be common because of the frequency of code using (expression) &#8211; 1  </p>
<p>for-instance..</p>
<p>..given a pointer to buffer and its size the last item is at (pointer + size) &#8211; 1 </p>
<p>..the previous item in an array is at (index) &#8211; 1</p>
<p>Also I dont agree with the conjecture that most loops are from 0 (or 1) to n..</p>
<p>..most loops are simply repeated &#8216;n&#8217; times .. thus &#8216;n&#8217; itself can be used as the counter, requiring only 1 register of overhead instead of the 2 registers needed for &#8216;0 to n&#8217; style loops.</p>
<p>If you are suprised that C compilers can turn your 0 to n style loop into something different, think again. Modern compilers will even turn code using several incrementing/decrementing pointers into code using a single incrementing/decrementing pointer plus an invariant displacement. Same number of registers needed, but only one increment per iteration instead of 2 or more.</p>
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		<title>By: Hohums</title>
		<link>http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-649</link>
		<dc:creator>Hohums</dc:creator>
		<pubDate>Tue, 09 Oct 2007 07:00:59 +0000</pubDate>
		<guid isPermaLink="false">http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-649</guid>
		<description>In regards to Dec.  My theory is that a lot of the standard library strings and array operations are in reverse.  Also when doing implicit memory copies the compiler may apply the optimization there. 

A easy way to figure out what is happening is figure out what operations are generally around the dec call.</description>
		<content:encoded><![CDATA[<p>In regards to Dec.  My theory is that a lot of the standard library strings and array operations are in reverse.  Also when doing implicit memory copies the compiler may apply the optimization there. </p>
<p>A easy way to figure out what is happening is figure out what operations are generally around the dec call.</p>
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		<title>By: Dru&#8217;s Blog &#187; Blog Archive &#187; x86 instruction diversity</title>
		<link>http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-62</link>
		<dc:creator>Dru&#8217;s Blog &#187; Blog Archive &#187; x86 instruction diversity</dc:creator>
		<pubDate>Mon, 25 Jun 2007 08:48:29 +0000</pubDate>
		<guid isPermaLink="false">http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-62</guid>
		<description>[...] someone did a naive analysis of x86 instruction diversity in typical binaries, I had my suspicions. I have looked at enough [...]</description>
		<content:encoded><![CDATA[<p>[...] someone did a naive analysis of x86 instruction diversity in typical binaries, I had my suspicions. I have looked at enough [...]</p>
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		<title>By: Sol</title>
		<link>http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-30</link>
		<dc:creator>Sol</dc:creator>
		<pubDate>Sun, 29 Apr 2007 15:02:31 +0000</pubDate>
		<guid isPermaLink="false">http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-30</guid>
		<description>Actually the SSE is heavily used in Multimedia applications especially games. Also the latest MSVC compiler uses SSE (scalar) instructions for float operations. Data about this can only be obtained by getting dynamic analysis of applications.</description>
		<content:encoded><![CDATA[<p>Actually the SSE is heavily used in Multimedia applications especially games. Also the latest MSVC compiler uses SSE (scalar) instructions for float operations. Data about this can only be obtained by getting dynamic analysis of applications.</p>
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		<title>By: marcuscf</title>
		<link>http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-29</link>
		<dc:creator>marcuscf</dc:creator>
		<pubDate>Sun, 29 Apr 2007 04:20:32 +0000</pubDate>
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		<description>That&#039;s really interesting!
Considering that Intel and AMD are constantly adding instructions to their processors, I have always wondered if all those new and shiny SSE, SSE2, SSE999, etc. are really used by common software or if those parts of the chip stay idle most of time. Do you have any data about it? :-)</description>
		<content:encoded><![CDATA[<p>That&#8217;s really interesting!<br />
Considering that Intel and AMD are constantly adding instructions to their processors, I have always wondered if all those new and shiny SSE, SSE2, SSE999, etc. are really used by common software or if those parts of the chip stay idle most of time. Do you have any data about it? <img src='http://s.wordpress.com/wp-includes/images/smilies/icon_smile.gif' alt=':-)' class='wp-smiley' /> </p>
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		<title>By: skies1239</title>
		<link>http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-28</link>
		<dc:creator>skies1239</dc:creator>
		<pubDate>Sun, 29 Apr 2007 02:05:48 +0000</pubDate>
		<guid isPermaLink="false">http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-28</guid>
		<description>.....</description>
		<content:encoded><![CDATA[<p>&#8230;..</p>
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		<title>By: Javier Aroche</title>
		<link>http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-27</link>
		<dc:creator>Javier Aroche</dc:creator>
		<pubDate>Sat, 28 Apr 2007 21:53:44 +0000</pubDate>
		<guid isPermaLink="false">http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-27</guid>
		<description>Well there is a lot of &lt;em&gt;dupe&lt;/em&gt; opcodes, but optimized for the first register, ax.</description>
		<content:encoded><![CDATA[<p>Well there is a lot of <em>dupe</em> opcodes, but optimized for the first register, ax.</p>
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		<title>By: Dave</title>
		<link>http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-26</link>
		<dc:creator>Dave</dc:creator>
		<pubDate>Sat, 28 Apr 2007 19:53:50 +0000</pubDate>
		<guid isPermaLink="false">http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-26</guid>
		<description>Years ago, I read some alternate codes...:
http://ruthless.zathras.de/fun/top-secret/NewOpCodes.txt

Such a list makes me wonder just how close to reality they were. :)</description>
		<content:encoded><![CDATA[<p>Years ago, I read some alternate codes&#8230;:<br />
<a href="http://ruthless.zathras.de/fun/top-secret/NewOpCodes.txt" rel="nofollow">http://ruthless.zathras.de/fun/top-secret/NewOpCodes.txt</a></p>
<p>Such a list makes me wonder just how close to reality they were. <img src='http://s.wordpress.com/wp-includes/images/smilies/icon_smile.gif' alt=':)' class='wp-smiley' /> </p>
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		<title>By: Ngadutrafik 2007</title>
		<link>http://bloggablea.wordpress.com/2007/04/27/so-does-anyone-even-use-all-these-darn-cpu-instructions/#comment-25</link>
		<dc:creator>Ngadutrafik 2007</dc:creator>
		<pubDate>Sat, 28 Apr 2007 19:12:22 +0000</pubDate>
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		<description>This is the BEST Computer&#039;s Coding ilustration !
thanks for your post

Best Regards...
&lt;b&gt;&lt;a href=&quot;http://ngadutrafik2007.isgreat.org/&quot; rel=&quot;nofollow&quot;&gt;ngadutrafik 2007&lt;/a&gt;&lt;/b&gt;</description>
		<content:encoded><![CDATA[<p>This is the BEST Computer&#8217;s Coding ilustration !<br />
thanks for your post</p>
<p>Best Regards&#8230;<br />
<b><a href="http://ngadutrafik2007.isgreat.org/" rel="nofollow">ngadutrafik 2007</a></b></p>
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	</item>
</channel>
</rss>
